Multitudes of multiprocessor systems including a plurality of processors sharing a memory have been applied in various industrial fields. As a recent technical trend of system LSI, there is actively used a multi-core architecture loaded with a plurality of processor cores. Particularly, in an embedded system LSI, it is often advantageous to load a plurality of processor cores of medium scale or smaller, rather than loading one ultra-high speed processor core, in the aspect of cost, electric power consumption, and the like.
For instance, patent literature 1 and patent literature 2 disclose methods, wherein a plurality of identical processors are loaded, and the number of processors to be operated is determined depending on a load or a calorific value required in executing a program, as an electric power consumption reduction technology in a multiprocessor system and a multi-core LSI loaded with a plurality of processors (hereinafter, “a processor” and “a processor core” are generically called as a “processor”).
In patent literature 1, an input command is decoded, and in the case where the number of computations to be executed in parallel is smaller than the number of processors, an operational clock signal of a processor in an inoperative state is suspended. Thereby, unwanted electric power consumption is suppressed, as necessary.
On the other hand, patent literature 2 discloses a method, wherein the degree of parallel use of a plurality of processors provided in a multiprocessor system and a multi-core LSI is switched depending on a temperature. In patent literature 2, the number of processors to be operated is determined so that a required calorific value is equal to or smaller than a predetermined calorific value. A calorific value may be interpreted as an electric power consumption. Thus, programs can always be run in parallel in a predetermined electric power consumption range.
Patent literature 3 discloses a method, wherein different processors (a main processor and a sub processor) are prepared to allocate programs by function distribution, and some of the programs are run only by the sub processor during a power saving operation time. Only in a condition that a program which is not allocated to the sub processor is required to be run e.g. a sophisticated error correcting process is performed, an electric power is supplied to the main processor to allow the main processor to execute the process. This enables to shorten an operation time of the main processor, thereby reducing the electric power consumption.
In a mobile-embedded computing system as represented by e.g. a mobile phone and a mobile terminal, electric power consumption reduction is an important issue, as well as enhancing the function and the performance of the system. Particularly, as described above, in an embedded system LSI, a multi-core architecture loaded with a plurality of processor cores of medium scale or smaller is selected, rather than loading one ultra-high speed processor core, in the aspect of cost, electric power consumption, and the like.
As recited in patent literature 1 and patent literature 2, normally, in a multiprocessor system or a multi-core LSI called as VLIW (Very Long Instruction Word) or SMP (Symmetric Multi Processor), a plurality of identical processors are prepared, and the number of processors to be operated is determined depending on the degree of parallelism of programs. In this arrangement, preparing a large number of (ten or more) low-performance processors only results in increasing the overhead. There is an increasing demand for loading several (two to four) processors of medium scale or larger in the aspect of performance. Accordingly, even if a load of a program to be executed is reduced, and electric power supply to the processors other than one processor is suspended, since the electric power consumption of the one processor is relatively high, a required electric power consumption is increased to some extent.
In a homogeneous architecture such as VLIW and SMP, any one of the programs may be executed by any one of the processors. Therefore, there should be no difference in e.g. instruction set and memory map between the processors. For instance, it is difficult to apply a low-power consumption processor architecture to only a processor or processors which should be kept in an operated state. On the other hand, in the case where there is a difference between the processors, it is necessary to determine in advance which program, out of a plurality of programs, is to be run on which processor. Patent literature 3 recites an electric power consumption reduction technology to be applied in the case where processors are not homogeneous.
In the case where the technology recited in patent literature 3 is used, only the sub processor is operated during a power saving operation time. Accordingly, selecting a relatively low-performance and low-power consumption processor architecture as the sub processor enables to reduce the electric power consumption during a power saving operation time, as compared with the technologies recited in patent literature 1 and patent literature 2. The technology recited in patent literature 3 is a technology capable of reducing the electric power consumption during a power saving operation time by allocating a program to be mainly executed during the power saving operation time to the sub processor, and allocating a program to be run at a high speed to the high-performance main processor.
There is a case, however, that a program allocated to the main processor is required to be operated even in a power saving operation time due to an influence of e.g. an external event. In this case, a control flow of supplying an electric power to the high-performance main processor, waiting for stabilization, executing a program, and cutting off the electric power supply is necessary, which may fail to achieve electric power consumption reduction, as expected. In particular, a program which should be run during a power saving operation time, and should be quickly started up in a high-speed operation time, is required to be loaded in the high-performance main processor, which hinders the electric power consumption reduction.
In the following, a clock display process to be executed in e.g. a mobile phone is described. In a recently-available mobile phone, as Java (registered trademark) and a browsing software are loaded, and various functions are developed, a high-speed screen rendering process is required. If an architecture provided with heterogeneous processors as described above is employed, generally, a screen rendering process is allocated to a high-performance main processor. However, in executing the clock display process, the screen rendering process is required to be executed periodically (every one second or every one minute), even if the mobile phone is in a call wait state (a state that no manipulation is conducted). In other words, it is necessary to periodically activate the high-performance main processor, even in a condition that the call wait state is continued for a long time. This may lower the electric power consumption reducing effect.
patent literature 1: JP 2001-92661A (pages 4 through 11, FIGS. 1 through 12)
patent literature 2: JP2006-11548A (pages 6 through 13, FIGS. 1 through 12)
patent literature 3; JP Hei 7-13787A (pages 3 through 4, FIGS. 1 through 3)